This invention relates generally to semiconductor processing and, particularly, to forming interlayer dielectric materials.
Conventional integrated circuits may include an interconnect metal layer which is made up of a large number of metal interconnects. Each of these interconnects may carry signals. Each signal on each interconnect may be affected by line to line capacitance due to adjacent interconnects.
As feature size dramatically decreases, particularly below 1 micron, the contribution to overall capacitance due to line to line capacitance dramatically increases. At the same time, the contribution of layer to layer capacitance dramatically decreases.
Thus, there is a need for better ways to reduce the line to line capacitance of integrated circuits.